Abstract
System-level thermal management techniques normally map applications on non-Adjacent cores to guarantee the safe temperature in many-core systems, while the communication efficiency will be oppositely affected by long-distance data transmission over conventional Network-on-Chips (NoC). SMART NoC has enabled single-cycle multi-hop bypass channels between distant cores, which can significantly reduce inter-processor communication latency. However, communication efficiency of SMART will be significantly diminished by express bypass break due to communication conflict. In order to achieve communication optimization with guaranteed system thermal reliability, we propose a dynamic reconfiguration method for logical interconnection topology through task mapping on top of SMART NoC. Active cores are physically decentralized on chip for better heat dissipation, while communication overhead can be reduced by minimized communication conflict and maximized bypass routing. Applicability and effectiveness of the proposed technique can be improved with significant achievements in reducing communication overhead and improving application performance, compared with state-of-The-Art techniques.
Original language | English |
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Title of host publication | 2017 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2017 |
Publisher | IEEE |
ISBN (Electronic) | 9781450351850 |
DOIs | |
Publication status | Published - 7 Nov 2017 |
Event | 2017 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2017 - Seoul, Korea, Republic of Duration: 15 Oct 2017 → 20 Oct 2017 |
Conference
Conference | 2017 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2017 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 15/10/17 → 20/10/17 |
ASJC Scopus subject areas
- Hardware and Architecture
- Information Systems
- Software