WCET analysis with MRU cache: Challenging LRU for predictability

Nan Guan, Mingsong Lv, Wang Yi, Ge Yu

Research output: Journal article publicationJournal articleAcademic researchpeer-review

7 Citations (Scopus)

Abstract

Most previous work on cache analysis for WCET estimation assumes a particular replacement policy called LRU. In contrast, much less work has been done for non-LRU policies, since they are generally considered to be very unpredictable. However, most commercial processors are actually equipped with these non-LRU policies, since they are more efficient in terms of hardware cost, power consumption and thermal output, while still maintaining almost as good average-case performance as LRU. In this work, we study the analysis of MRU, a non-LRU replacement policy employed in mainstream processor architectures like Intel Nehalem. Our work shows that the predictability of MRU has been significantly underestimated before, mainly because the existing cache analysis techniques and metrics do not match MRU well. As our main technical contribution, we propose a new cache hit/miss classification, κ-Miss, to better capture the MRU behavior, and develop formal conditions and efficient techniques to decide κ-Miss memory accesses. A remarkable feature of our analysis is that the κ-Miss classifications under MRU are derived by the analysis result of the same program under LRU. Therefore, our approach inherits the advantages in efficiency and precision of the state-of-the-art LRU analysis techniques based on abstract interpretation. Experiments with instruction caches show that our proposed MRU analysis has both good precision and high efficiency, and the obtained estimated WCET is rather close to (typically 1% ∼8% more than) that obtained by the state-of-the-art LRU analysis, which indicates that MRU is also a good candidate for cache replacement policies in real-time systems.
Original languageEnglish
Article number123
JournalTransactions on Embedded Computing Systems
Volume13
Issue number4 SPEC. ISSUE
DOIs
Publication statusPublished - 1 Jan 2014
Externally publishedYes

Keywords

  • Cache replacement
  • Hard real time
  • MRU
  • Worst-case execution times

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture

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