TY - GEN
T1 - Toward High-mobility and Low-power 2D MoS
2
Field-effect Transistors
AU - Yu, Zhihao
AU - Zhu, Ying
AU - Li, Weisheng
AU - Shi, Yi
AU - Zhang, Gang
AU - Chai, Yang
AU - Wang, Xinran
PY - 2019/1/16
Y1 - 2019/1/16
N2 -
2D semiconductors are promising candidates for future electronic device applications due to their immunity to short-channel effects (SCE), but many issues regarding mobility, contact, interface and power consumption still remain (Fig. 1). We develop a low-field model to calculate the mobility of monolayer MoS
2
FETs. Guided by the model, high carrier mobility of 150 cm
2
/Vs and saturation current over 450 μ Aμm are realized in long-channel monolayer MoS
2
FETs, through a series of interface optimization by high- κ dielectric and thiol chemical treatment. For low-power applications, we demonstrate hysteresis-free MoS
2
negative capacitance FETs (NCFETs) using ferroelectric HtZrO
x
(HZO) as gate dielectric, achieving sub-60m V/dec subthreshold slope (SS) over 6 orders of I
D
, minimum SS of 24 mV/dec and 10
7
on/off ratio under V dd=0.5 V. We further study the high frequency performance and show that sub-60mV/dec is maintained at least to 10 kHz without signs of degradation. Finally, by performing different gate sweeps we conclude that the steep slope is indeed due to NC effects rather than ferroelectric switching of HZO.
AB -
2D semiconductors are promising candidates for future electronic device applications due to their immunity to short-channel effects (SCE), but many issues regarding mobility, contact, interface and power consumption still remain (Fig. 1). We develop a low-field model to calculate the mobility of monolayer MoS
2
FETs. Guided by the model, high carrier mobility of 150 cm
2
/Vs and saturation current over 450 μ Aμm are realized in long-channel monolayer MoS
2
FETs, through a series of interface optimization by high- κ dielectric and thiol chemical treatment. For low-power applications, we demonstrate hysteresis-free MoS
2
negative capacitance FETs (NCFETs) using ferroelectric HtZrO
x
(HZO) as gate dielectric, achieving sub-60m V/dec subthreshold slope (SS) over 6 orders of I
D
, minimum SS of 24 mV/dec and 10
7
on/off ratio under V dd=0.5 V. We further study the high frequency performance and show that sub-60mV/dec is maintained at least to 10 kHz without signs of degradation. Finally, by performing different gate sweeps we conclude that the steep slope is indeed due to NC effects rather than ferroelectric switching of HZO.
UR - http://www.scopus.com/inward/record.url?scp=85061841355&partnerID=8YFLogxK
U2 - 10.1109/IEDM.2018.8614644
DO - 10.1109/IEDM.2018.8614644
M3 - Conference article published in proceeding or book
AN - SCOPUS:85061841355
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 22.4.1-22.4.4
BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th Annual IEEE International Electron Devices Meeting, IEDM 2018
Y2 - 1 December 2018 through 5 December 2018
ER -