Timing optimization of nested loops considering code size for DSP applications

Qingfeng Zhuge, Zili Shao, Edwin H.M. Sha

Research output: Journal article publicationConference articleAcademic researchpeer-review

2 Citations (Scopus)

Abstract

Software pipelining for nested loops remains a challenging problem for embedded system design. The existing software pipelining techniques for single loops can only explore the parallelism of the innermost loop, so the final timing performance is inferior. While multi-dimensional (MD) retiming can explore the outer loop parallelism, it introduces large overheads in loop index generation and code size due to transformation. In this paper, we use MD retiming to model the software pipelining problem of nested loops. We show that the computation time and code size of a software-pipelined loop nest is affected by execution sequence and retiming function. The algorithm of Software Pipelining for NEsted loops technique (SPINE) is proposed to generate fully parallelized loops efficiently with the overheads as small as possible. The experimental results show that our technique outperforms both the standard software pipelining and MD retiming significantly.
Original languageEnglish
Pages (from-to)475-482
Number of pages8
JournalProceedings of the International Conference on Parallel Processing
Publication statusPublished - 17 Dec 2004
Externally publishedYes
EventProceedings - 2004 International Conference on Parallel Processing, ICPP 2004 - Montreal, Que, Canada
Duration: 15 Aug 200418 Aug 2004

ASJC Scopus subject areas

  • Hardware and Architecture
  • Engineering(all)

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