Threshold Voltage Model for Deep-Submicrometer Fully Depleted SOI MOSFET's

Srinivasa R. Banna, Philip Ching Ho Chan, Ping K. Ko, Cuong T. Nguyen, Mansun Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review

90 Citations (Scopus)

Abstract

The threshold voltage, Vth of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the Vth roll-off and drain voltage dependence. The shift in threshold voltage has a similar trend as in bulk. However, threshold voltage roll-off in FDSOI is less than bulk for the same effective channel length as predicted by a shorter characteristic length / in FDSOI. Furthermore, δth is independent of back-gate bias in FDSOI MOSFET. Experimental data shows that the model predictions are in good agreement. The proposed model retains accuracy because it does not assume apriori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, Vth design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between model predicted Vth design space and previously reported two-dimensional numerical simulations using MINIMOS5 [17] is obtained.
Original languageEnglish
Pages (from-to)1949-1955
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume42
Issue number11
DOIs
Publication statusPublished - 1 Jan 1995
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Physics and Astronomy (miscellaneous)

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