Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material

Philip Ching Ho Chan; Xusheng Wu; Shengdong Zhang; Chuguang Feng; Mansun Chan

Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material

Philip Ching Ho Chan
, Xusheng Wu
, Shengdong Zhang
, Chuguang Feng
, Mansun Chan

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

3 Citations (Scopus)

Abstract

In this work, a Stacked 3-D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2-D architecture: (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2-D CMOS technology. To implement the 3-D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3-D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.

Original language	English
Title of host publication	International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
Pages	81-85
Number of pages	5
Publication status	Published - 1 Dec 2004
Externally published	Yes
Event	2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China Duration: 18 Oct 2004 → 21 Oct 2004

Conference

Conference	2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
Country/Territory	China
City	Beijing
Period	18/10/04 → 21/10/04

ASJC Scopus subject areas

General Engineering

Cite this

@inproceedings{69e23411f611411da8bd820fbfd366f6,

title = "Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material",

abstract = "In this work, a Stacked 3-D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50\% area reduction compared to the conventional 2-D architecture: (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2-D CMOS technology. To implement the 3-D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3-D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.",

author = "Chan, \{Philip Ching Ho\} and Xusheng Wu and Shengdong Zhang and Chuguang Feng and Mansun Chan",

year = "2004",

month = dec,

day = "1",

language = "English",

pages = "81--85",

booktitle = "International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT",

note = "2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 ; Conference date: 18-10-2004 Through 21-10-2004",

}

Chan, PCH, Wu, X, Zhang, S, Feng, C & Chan, M 2004, Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material. in International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT. pp. 81-85, 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004, Beijing, China, 18/10/04.

Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material. / Chan, Philip Ching Ho; Wu, Xusheng; Zhang, Shengdong et al.
International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT. 2004. p. 81-85.

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

TY - GEN

T1 - Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material

AU - Chan, Philip Ching Ho

AU - Wu, Xusheng

AU - Zhang, Shengdong

AU - Feng, Chuguang

AU - Chan, Mansun

PY - 2004/12/1

Y1 - 2004/12/1

N2 - In this work, a Stacked 3-D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2-D architecture: (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2-D CMOS technology. To implement the 3-D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3-D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.

AB - In this work, a Stacked 3-D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2-D architecture: (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2-D CMOS technology. To implement the 3-D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3-D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.

UR - https://www.scopus.com/pages/publications/21644443169

M3 - Conference article published in proceeding or book

SP - 81

EP - 85

BT - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

T2 - 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

Y2 - 18 October 2004 through 21 October 2004

ER -

Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material

Abstract

Conference

ASJC Scopus subject areas

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