Abstract
In this work, a Stacked 3-D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2-D architecture: (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2-D CMOS technology. To implement the 3-D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3-D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.
Original language | English |
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Title of host publication | International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT |
Pages | 81-85 |
Number of pages | 5 |
Publication status | Published - 1 Dec 2004 |
Externally published | Yes |
Event | 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China Duration: 18 Oct 2004 → 21 Oct 2004 |
Conference
Conference | 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 |
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Country/Territory | China |
City | Beijing |
Period | 18/10/04 → 21/10/04 |
ASJC Scopus subject areas
- General Engineering