Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material

Philip Ching Ho Chan, Xusheng Wu, Shengdong Zhang, Chuguang Feng, Mansun Chan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

3 Citations (Scopus)

Abstract

In this work, a Stacked 3-D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2-D architecture: (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2-D CMOS technology. To implement the 3-D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3-D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.
Original languageEnglish
Title of host publicationInternational Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT
Pages81-85
Number of pages5
Publication statusPublished - 1 Dec 2004
Externally publishedYes
Event2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004 - Beijing, China
Duration: 18 Oct 200421 Oct 2004

Conference

Conference2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004
CountryChina
CityBeijing
Period18/10/0421/10/04

ASJC Scopus subject areas

  • Engineering(all)

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