Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization

Victor W.C. Chan, Philip Ching Ho Chan, Mansun Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review

31 Citations (Scopus)

Abstract

A three-dimensional (3-D) CMOS integrated circuit was fabricated based on the conventional CMOS SOI technology. The first layer of transistors was formed on the SOI. The second layer of transistors was built on large-grain polysilicon-on-insulator (LPSOI). The recrystallized film was formed by the recrystallization of amorphous silicon using metal-induced lateral crystallization (MILC). The devices from the lower and upper layers were characterized and the result indicated that the SOI and LPSOI devices have similar electrical characteristics. The 3-D circuit design and layout considerations will be introduced. The 3-D CMOS inverters were demonstrated with p-channel devices stacking over the n-channel ones. The ring-oscillator showed that the 3-D circuit has 30 % reduction in the layout area and it operated at power supply as low as 0.5 V. The lower propagation delay and load capacitance suggest that 3-D circuit has higher performance than the conventional two-dimensional (2-D) circuit.
Original languageEnglish
Pages (from-to)1394-1399
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume48
Issue number7
DOIs
Publication statusPublished - 1 Jul 2001
Externally publishedYes

Keywords

  • 3-D integrated circuits
  • Metal-induced lateral crystallization
  • SOI
  • Thin film transistors

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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