Three dimensional CMOS integrated circuits on large grain polysilicon films

V. W C Chan; Philip Ching Ho Chan; M. Chan

Three dimensional CMOS integrated circuits on large grain polysilicon films

V. W C Chan, Philip Ching Ho Chan, M. Chan

Research output: Journal article publication › Conference article › Academic research › peer-review

Abstract

In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.

Original language	English
Pages (from-to)	161-164
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 1 Dec 2000
Externally published	Yes
Event	2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 10 Dec 2000 → 13 Dec 2000

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Three dimensional CMOS integrated circuits on large grain polysilicon films",

abstract = "In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.",

author = "Chan, {V. W C} and Chan, {Philip Ching Ho} and M. Chan",

year = "2000",

month = dec,

day = "1",

language = "English",

pages = "161--164",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

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note = "2000 IEEE International Electron Devices Meeting ; Conference date: 10-12-2000 Through 13-12-2000",

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TY - JOUR

T1 - Three dimensional CMOS integrated circuits on large grain polysilicon films

AU - Chan, V. W C

AU - Chan, Philip Ching Ho

AU - Chan, M.

PY - 2000/12/1

Y1 - 2000/12/1

N2 - In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.

AB - In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.

UR - http://www.scopus.com/inward/record.url?scp=0034453375&partnerID=8YFLogxK

M3 - Conference article

SP - 161

EP - 164

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

SN - 0163-1918

T2 - 2000 IEEE International Electron Devices Meeting

Y2 - 10 December 2000 through 13 December 2000

ER -

Three dimensional CMOS integrated circuits on large grain polysilicon films

Abstract

ASJC Scopus subject areas

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