Three dimensional CMOS integrated circuits on large grain polysilicon films

V. W C Chan, Philip Ching Ho Chan, M. Chan

Research output: Journal article publicationConference articleAcademic researchpeer-review

33 Citations (Scopus)

Abstract

In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.
Original languageEnglish
Pages (from-to)161-164
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1 Dec 2000
Externally publishedYes
Event2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States
Duration: 10 Dec 200013 Dec 2000

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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