Abstract
In this paper, we report high performance three-dimensional (3-D) CMOS integrated circuits. The first layer of transistors is fabricated on Silicon-on-Insulator (SOI) and second layer is fabricated on large-gain polysilicon-on-insulator (LPSOI) film, with oxide as the interlayer dielectric. The LPSOI film is formed by the re-crystallization of amorphous silicon through metal-induced lateral crystallization (MILC) at an elevated temperature. Compared with the conventional 2-D CMOS SOI low-voltage circuit, 3D circuit shows significant reduction in circuit area, shorter propagation delay and lower dynamic power consumption.
Original language | English |
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Pages (from-to) | 161-164 |
Number of pages | 4 |
Journal | Technical Digest - International Electron Devices Meeting |
Publication status | Published - 1 Dec 2000 |
Externally published | Yes |
Event | 2000 IEEE International Electron Devices Meeting - San Francisco, CA, United States Duration: 10 Dec 2000 → 13 Dec 2000 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering