Theoretical examination of the circuit requirements of power factor correction

Chi Kong Tse, M. H L Chow

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

21 Citations (Scopus)

Abstract

In the first part of the paper, the requirements of circuits containing linear inductors, capacitors and ideal switches for the synthesis of power-factor-correction (PFC) converters are examined. Sufficient conditions for achieving PFC are stated in terms of the circuit topology and the switching sequence. Various topologies, from the simplest buck, boost, and buck-boost converters to fourth-order Cuk, Zeta and SEPIC converters, are examined in the light of these topological conditions. In the second part of the paper, the general configuration of power supplies that provide PFC and voltage regulation will be discussed. It consists of two simple power stages forming a three-port network which is terminated to an input voltage, a storage capacitor and an output load. The various possible arrangements of the two constituent power stages will be discussed with emphasis on minimizing the amount of power that is processed serially by the power stages.
Original languageEnglish
Title of host publicationPESC Record - IEEE Annual Power Electronics Specialists Conference
Pages1415-1421
Number of pages7
Volume2
DOIs
Publication statusPublished - 1 Jan 1998
EventProceedings of the 1998 IEEE 29th Annual Power Electronics Specialists Conference, PESC. Part 2 (of 2) - Fukuoka, Japan
Duration: 18 May 199821 May 1998

Conference

ConferenceProceedings of the 1998 IEEE 29th Annual Power Electronics Specialists Conference, PESC. Part 2 (of 2)
CountryJapan
CityFukuoka
Period18/05/9821/05/98

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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