The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistors

Victor W C Chan, Philip Ching Ho Chan, Chunshan Yin

Research output: Journal article publicationJournal articleAcademic researchpeer-review

34 Citations (Scopus)

Abstract

High-performance low-voltage thin-film transistors (TFTs) can be fabricated by grain-enhancement methods such as nickel-seeded metal-induced lateral crystallization (MILC). Electrical characteristics of the TFTs may vary due to the existence of the grain boundaries in the device active region. To obtain the best device characteristics, the effect of grain boundaries on the device must be investigated. In this paper, the cumulative distributions of the device properties such as leakage current, threshold voltage, subthreshold slope, and field-effect mobility as a function of different channel lengths and widths were studied. In general, the grain boundary effects decrease with device size. Devices with short channel lengths and wide channel widths may suffer from degradation due to large leakage current. Moreover, the effects due to the location of the nickel-seeding region on device characteristics were investigated. These include the effect of the longitudinal and lateral grain boundaries and the distance between the nickel seeding region and the device. Finally, a design guideline to reduce the grain boundary effect is presented.
Original languageEnglish
Pages (from-to)1384-1391
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume49
Issue number8
DOIs
Publication statusPublished - 1 Aug 2002
Externally publishedYes

Keywords

  • Amorphous material
  • Grain boundary
  • Metal-induced lateral crystallization (MILC)
  • Silicon-on-insulator (SOI)
  • Thin-film transistor (TFT)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

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