TY - GEN
T1 - The design and evaluation of a selective way based trace cache
AU - Zeng, Deze
AU - Guo, Minyi
AU - Guo, Song
AU - Dong, Mianxiong
AU - Jin, Hai
PY - 2009/11/9
Y1 - 2009/11/9
N2 - Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of instructions per cycle.
AB - Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of instructions per cycle.
KW - Computer architecture
KW - Energy efficient
KW - Instruction fetch unit design
KW - Selective way
KW - Trace cache
UR - https://www.scopus.com/pages/publications/70350627234
U2 - 10.1007/978-3-642-03644-6_8
DO - 10.1007/978-3-642-03644-6_8
M3 - Conference article published in proceeding or book
SN - 3642036430
SN - 9783642036439
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 95
EP - 109
BT - Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings
T2 - 8th International Symposium on Advanced Parallel Processing Technologies, APPT 2009
Y2 - 24 August 2009 through 25 August 2009
ER -
