The design and evaluation of a selective way based trace cache

Deze Zeng; Minyi Guo; Song Guo; Mianxiong Dong; Hai Jin

doi:10.1007/978-3-642-03644-6_8

The design and evaluation of a selective way based trace cache

Deze Zeng
, Minyi Guo
, Song Guo
, Mianxiong Dong
, Hai Jin

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

1 Citation (Scopus)

Abstract

Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of instructions per cycle.

Original language	English
Title of host publication	Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings
Pages	95-109
Number of pages	15
DOIs	https://doi.org/10.1007/978-3-642-03644-6_8
Publication status	Published - 9 Nov 2009
Externally published	Yes
Event	8th International Symposium on Advanced Parallel Processing Technologies, APPT 2009 - Rapperswil, Switzerland Duration: 24 Aug 2009 → 25 Aug 2009

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	5737 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	8th International Symposium on Advanced Parallel Processing Technologies, APPT 2009
Country/Territory	Switzerland
City	Rapperswil
Period	24/08/09 → 25/08/09

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Computer architecture
Energy efficient
Instruction fetch unit design
Selective way
Trace cache

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

More information

10.1007/978-3-642-03644-6_8

Cite this

Zeng, D., Guo, M., Guo, S., Dong, M., & Jin, H. (2009). The design and evaluation of a selective way based trace cache. In Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings (pp. 95-109). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5737 LNCS). https://doi.org/10.1007/978-3-642-03644-6_8

@inproceedings{fbc8a47829024a508a91e76921b7b4e7,

title = "The design and evaluation of a selective way based trace cache",

abstract = "Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1\% on average, while providing almost the same performance in terms of number of instructions per cycle.",

keywords = "Computer architecture, Energy efficient, Instruction fetch unit design, Selective way, Trace cache",

author = "Deze Zeng and Minyi Guo and Song Guo and Mianxiong Dong and Hai Jin",

year = "2009",

month = nov,

day = "9",

doi = "10.1007/978-3-642-03644-6\_8",

language = "English",

isbn = "3642036430",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "95--109",

booktitle = "Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings",

note = "8th International Symposium on Advanced Parallel Processing Technologies, APPT 2009 ; Conference date: 24-08-2009 Through 25-08-2009",

}

Zeng, D, Guo, M, Guo, S, Dong, M & Jin, H 2009, The design and evaluation of a selective way based trace cache. in Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 5737 LNCS, pp. 95-109, 8th International Symposium on Advanced Parallel Processing Technologies, APPT 2009, Rapperswil, Switzerland, 24/08/09. https://doi.org/10.1007/978-3-642-03644-6_8

The design and evaluation of a selective way based trace cache. / Zeng, Deze; Guo, Minyi; Guo, Song et al.
Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings. 2009. p. 95-109 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 5737 LNCS).

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

TY - GEN

T1 - The design and evaluation of a selective way based trace cache

AU - Zeng, Deze

AU - Guo, Minyi

AU - Guo, Song

AU - Dong, Mianxiong

AU - Jin, Hai

PY - 2009/11/9

Y1 - 2009/11/9

N2 - Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of instructions per cycle.

AB - Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of instructions per cycle.

KW - Computer architecture

KW - Energy efficient

KW - Instruction fetch unit design

KW - Selective way

KW - Trace cache

UR - https://www.scopus.com/pages/publications/70350627234

U2 - 10.1007/978-3-642-03644-6_8

DO - 10.1007/978-3-642-03644-6_8

M3 - Conference article published in proceeding or book

SN - 3642036430

SN - 9783642036439

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 95

EP - 109

BT - Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings

T2 - 8th International Symposium on Advanced Parallel Processing Technologies, APPT 2009

Y2 - 24 August 2009 through 25 August 2009

ER -

Zeng D, Guo M, Guo S, Dong M, Jin H. The design and evaluation of a selective way based trace cache. In Advanced Parallel Processing Technologies - 8th International Symposium, APPT 2009, Proceedings. 2009. p. 95-109. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-642-03644-6_8

The design and evaluation of a selective way based trace cache

Abstract

Publication series

Conference

UN SDGs

Keywords

ASJC Scopus subject areas

More information

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