Switching-activity minimization on instruction-level loop scheduling for VLIW DSP applications

Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin H.M. Sha

Research output: Journal article publicationConference articleAcademic researchpeer-review

2 Citations (Scopus)


This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.
Original languageEnglish
Pages (from-to)224-234
Number of pages11
JournalProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Publication statusPublished - 1 Dec 2004
Externally publishedYes
EventProceedings - 15th IEEE International Conference on Applications-Specific Systems, Architectures and Processors - Galveston, TX, United States
Duration: 27 Sep 200429 Sep 2004

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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