Switching-activity minimization on instruction-level loop scheduling for VLIW DSP applications

Zili Shao; Qingfeng Zhuge; Meilin Liu; Bin Xiao; Edwin H.M. Sha

Switching-activity minimization on instruction-level loop scheduling for VLIW DSP applications

Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin H.M. Sha

Research output: Journal article publication › Conference article › Academic research › peer-review

Abstract

This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.

Original language	English
Pages (from-to)	224-234
Number of pages	11
Journal	Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Publication status	Published - 1 Dec 2004
Externally published	Yes
Event	Proceedings - 15th IEEE International Conference on Applications-Specific Systems, Architectures and Processors - Galveston, TX, United States Duration: 27 Sept 2004 → 29 Sept 2004

ASJC Scopus subject areas

Hardware and Architecture
Computer Networks and Communications

Cite this

@article{6b2e11c83c674c1db13be30fa131f858,

title = "Switching-activity minimization on instruction-level loop scheduling for VLIW DSP applications",

abstract = "This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.",

author = "Zili Shao and Qingfeng Zhuge and Meilin Liu and Bin Xiao and Sha, {Edwin H.M.}",

year = "2004",

month = dec,

day = "1",

language = "English",

pages = "224--234",

journal = "Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors",

issn = "1063-6862",

publisher = "IEEE",

note = "Proceedings - 15th IEEE International Conference on Applications-Specific Systems, Architectures and Processors ; Conference date: 27-09-2004 Through 29-09-2004",

}

Switching-activity minimization on instruction-level loop scheduling for VLIW DSP applications. / Shao, Zili; Zhuge, Qingfeng; Liu, Meilin et al.
In: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, 01.12.2004, p. 224-234.

Research output: Journal article publication › Conference article › Academic research › peer-review

TY - JOUR

T1 - Switching-activity minimization on instruction-level loop scheduling for VLIW DSP applications

AU - Shao, Zili

AU - Zhuge, Qingfeng

AU - Liu, Meilin

AU - Xiao, Bin

AU - Sha, Edwin H.M.

PY - 2004/12/1

Y1 - 2004/12/1

N2 - This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.

AB - This paper develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (Switching-Activity Minimization Loop Scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.

UR - http://www.scopus.com/inward/record.url?scp=11244316785&partnerID=8YFLogxK

M3 - Conference article

SN - 1063-6862

SP - 224

EP - 234

JO - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

JF - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

T2 - Proceedings - 15th IEEE International Conference on Applications-Specific Systems, Architectures and Processors

Y2 - 27 September 2004 through 29 September 2004

ER -

Switching-activity minimization on instruction-level loop scheduling for VLIW DSP applications

Abstract

ASJC Scopus subject areas

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