This work develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (switching-activity minimization loop scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.
|International Conference on Application Specific Systems, Architectures and Processors (ASAP)
|International Conference on Application-specific Systems, Architectures and Processors [ASAP]
|1/01/04 → …
- Parallel architectures
- Processor scheduling
- Signal processing