Switching-activity minimization on instruction-level loop for VLIW DSP applications

Z. Shao, Q. Zhuge, M. Liu, Bin Xiao, E. Sha

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

Abstract

This work develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (switching-activity minimization loop scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.
Original languageEnglish
Title of host publication15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors : proceedings : September 27-29, 2004, Galveston, Texas
PublisherIEEE
Pages224-234
Number of pages11
ISBN (Print)0769522262
DOIs
Publication statusPublished - 2004
EventInternational Conference on Application-specific Systems, Architectures and Processors [ASAP] -
Duration: 1 Jan 2004 → …

Publication series

NameInternational Conference on Application Specific Systems, Architectures and Processors (ASAP)
ISSN (Print)2160-0511

Conference

ConferenceInternational Conference on Application-specific Systems, Architectures and Processors [ASAP]
Period1/01/04 → …

Keywords

  • Minimisation
  • Parallel architectures
  • Processor scheduling
  • Signal processing

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