@inproceedings{c309c8a4612b40f1b961375d619b80de,
title = "Switching-activity minimization on instruction-level loop for VLIW DSP applications",
abstract = "This work develops an instruction-level loop scheduling technique to reduce both execution time and bus switching activities for applications with loops on VLIW architectures. We propose an algorithm, SAMLS (switching-activity minimization loop scheduling), to minimize both schedule length and switching activities for applications with loops. In the algorithm, we obtain the best schedule from the ones that are generated from an initial schedule by repeatedly rescheduling the nodes with schedule length and switching activities minimization based on rotation scheduling and bipartite matching. The experimental results show that our algorithm can greatly reduce both schedule length and bus switching activities compared with the previous work.",
keywords = "Minimisation, Parallel architectures, Processor scheduling, Signal processing",
author = "Z. Shao and Q. Zhuge and M. Liu and Bin Xiao and E. Sha",
year = "2004",
doi = "10.1109/ASAP.2004.1342473",
language = "English",
isbn = "0769522262",
series = "International Conference on Application Specific Systems, Architectures and Processors (ASAP)",
publisher = "IEEE",
pages = "224--234",
booktitle = "15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors : proceedings : September 27-29, 2004, Galveston, Texas",
address = "United States",
note = "International Conference on Application-specific Systems, Architectures and Processors [ASAP] ; Conference date: 01-01-2004",
}