Study of nonlinear dynamics of LDPC decoders

Xia Zheng; Chung Ming Lau; Chi Kong Tse; Siu Chung Wong

doi:10.1109/ECCTD.2005.1523017

Study of nonlinear dynamics of LDPC decoders

Xia Zheng, Chung Ming Lau, Chi Kong Tse, Siu Chung Wong

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

2 Citations (Scopus)

Abstract

Low-density-parity-check (LDPC) codes have aroused much research interest because of their excellent bit error performance. The behaviour of the iterative LDPC decoders, however, has not been fully investigated at all signal-to-noise ratios (SNRs). By considering the LDPC decoders as high-dimensional nonlinear dynamical systems, we attempt to study the corresponding phase trajectories at different SNR values. By having an in-depth understanding of the decoder behaviour, engineers should be able to design more effective and efficient decoders.

Original language	English
Title of host publication	Proceedings of the 2005 European Conference on Circuit Theory and Design
Pages	157-160
Number of pages	4
Volume	2
DOIs	https://doi.org/10.1109/ECCTD.2005.1523017
Publication status	Published - 1 Dec 2005
Event	2005 European Conference on Circuit Theory and Design - Cork, Ireland Duration: 28 Aug 2005 → 2 Sep 2005

Conference

Conference	2005 European Conference on Circuit Theory and Design
Country/Territory	Ireland
City	Cork
Period	28/08/05 → 2/09/05

ASJC Scopus subject areas

Engineering(all)

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10.1109/ECCTD.2005.1523017

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AU - Tse, Chi Kong

AU - Wong, Siu Chung

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N2 - Low-density-parity-check (LDPC) codes have aroused much research interest because of their excellent bit error performance. The behaviour of the iterative LDPC decoders, however, has not been fully investigated at all signal-to-noise ratios (SNRs). By considering the LDPC decoders as high-dimensional nonlinear dynamical systems, we attempt to study the corresponding phase trajectories at different SNR values. By having an in-depth understanding of the decoder behaviour, engineers should be able to design more effective and efficient decoders.

AB - Low-density-parity-check (LDPC) codes have aroused much research interest because of their excellent bit error performance. The behaviour of the iterative LDPC decoders, however, has not been fully investigated at all signal-to-noise ratios (SNRs). By considering the LDPC decoders as high-dimensional nonlinear dynamical systems, we attempt to study the corresponding phase trajectories at different SNR values. By having an in-depth understanding of the decoder behaviour, engineers should be able to design more effective and efficient decoders.

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SN - 9780780390669

VL - 2

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EP - 160

BT - Proceedings of the 2005 European Conference on Circuit Theory and Design

T2 - 2005 European Conference on Circuit Theory and Design

Y2 - 28 August 2005 through 2 September 2005

ER -

Study of nonlinear dynamics of LDPC decoders

Abstract

Conference

ASJC Scopus subject areas

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