Abstract
A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.
| Original language | English |
|---|---|
| Pages (from-to) | 416-418 |
| Number of pages | 3 |
| Journal | IEEE Electron Device Letters |
| Volume | 26 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 1 Jun 2005 |
| Externally published | Yes |
Keywords
- CMOS
- Double SIMOX
- FinFET
- Silicon-on-insulator (SOI)
- Three-dimensional (3-D) integrated circuits
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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