Stacked 3-D fin-CMOS technology

Xusheng Wu, Philip Ching Ho Chan, Shengdong Zhang, Chuguang Feng, Mansun Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review

7 Citations (Scopus)


A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.
Original languageEnglish
Pages (from-to)416-418
Number of pages3
JournalIEEE Electron Device Letters
Issue number6
Publication statusPublished - 1 Jun 2005
Externally publishedYes


  • CMOS
  • Double SIMOX
  • FinFET
  • Silicon-on-insulator (SOI)
  • Three-dimensional (3-D) integrated circuits

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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