Stacked 3-D fin-CMOS technology

Xusheng Wu; Philip Ching Ho Chan; Shengdong Zhang; Chuguang Feng; Mansun Chan

doi:10.1109/LED.2005.848070

Stacked 3-D fin-CMOS technology

Xusheng Wu, Philip Ching Ho Chan, Shengdong Zhang, Chuguang Feng, Mansun Chan

Research output: Journal article publication › Journal article › Academic research › peer-review

10 Citations (Scopus)

Abstract

A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.

Original language	English
Pages (from-to)	416-418
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	26
Issue number	6
DOIs	https://doi.org/10.1109/LED.2005.848070
Publication status	Published - 1 Jun 2005
Externally published	Yes

Keywords

CMOS
Double SIMOX
FinFET
Silicon-on-insulator (SOI)
Three-dimensional (3-D) integrated circuits

ASJC Scopus subject areas

Electrical and Electronic Engineering

More information

10.1109/LED.2005.848070

Cite this

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title = "Stacked 3-D fin-CMOS technology",

abstract = "A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.",

keywords = "CMOS, Double SIMOX, FinFET, Silicon-on-insulator (SOI), Three-dimensional (3-D) integrated circuits",

author = "Xusheng Wu and Chan, {Philip Ching Ho} and Shengdong Zhang and Chuguang Feng and Mansun Chan",

year = "2005",

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AU - Wu, Xusheng

AU - Chan, Philip Ching Ho

AU - Zhang, Shengdong

AU - Feng, Chuguang

AU - Chan, Mansun

PY - 2005/6/1

Y1 - 2005/6/1

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AB - A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.

KW - CMOS

KW - Double SIMOX

KW - FinFET

KW - Silicon-on-insulator (SOI)

KW - Three-dimensional (3-D) integrated circuits

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 6

ER -

Stacked 3-D fin-CMOS technology

Abstract

Keywords

ASJC Scopus subject areas

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