Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs

Nan Guan, Qingxu Deng, Zonghua Gu, Wenyao Xu, Ge Yu

Research output: Journal article publicationJournal articleAcademic researchpeer-review

19 Citations (Scopus)


Field Programmable Gate Arrays (FPGAs) are very popular in today's embedded systems design, and Partial Runtime-Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this article, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bounds for several variants of global preemptive/nonpreemptive EDF scheduling, and compare the performance of different utilization bound tests.
Original languageEnglish
Article number56
JournalACM Transactions on Design Automation of Electronic Systems
Issue number4
Publication statusPublished - 1 Sept 2008
Externally publishedYes


  • FPGA
  • Real-time scheduling
  • Reconfigurable devices

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


Dive into the research topics of 'Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs'. Together they form a unique fingerprint.

Cite this