Abstract
Field Programmable Gate Arrays (FPGAs) are very popular in today's embedded systems design, and Partial Runtime-Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this article, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bounds for several variants of global preemptive/nonpreemptive EDF scheduling, and compare the performance of different utilization bound tests.
Original language | English |
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Article number | 56 |
Journal | ACM Transactions on Design Automation of Electronic Systems |
Volume | 13 |
Issue number | 4 |
DOIs | |
Publication status | Published - 1 Sept 2008 |
Externally published | Yes |
Keywords
- FPGA
- Real-time scheduling
- Reconfigurable devices
ASJC Scopus subject areas
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering