Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard

Qing Lu; Chiu Wing Sham; Chung Ming Lau

doi:10.1109/ASPDAC.2016.7427981

Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard

Qing Lu
, Chiu Wing Sham
, Chung Ming Lau

The Hong Kong Polytechnic University

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

12 Citations (Scopus)

Abstract

A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased to range from 382 MHz to 1852 MHz.

Original language	English
Title of host publication	2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Publisher	IEEE
Pages	19-20
Number of pages	2
Volume	25-28-January-2016
ISBN (Electronic)	9781467395694
ISBN (Print)	9781467395694
DOIs	https://doi.org/10.1109/ASPDAC.2016.7427981
Publication status	Published - 7 Mar 2016
Event	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao Duration: 25 Jan 2016 → 28 Jan 2016

Conference

Conference	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Country/Territory	Macao
City	Macao
Period	25/01/16 → 28/01/16

ASJC Scopus subject areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

More information

10.1109/ASPDAC.2016.7427981

Cite this

@inproceedings{c7eb497409fa4af98a9f082771c4c183,

title = "Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard",

abstract = "A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased to range from 382 MHz to 1852 MHz.",

author = "Qing Lu and Sham, \{Chiu Wing\} and Lau, \{Chung Ming\}",

year = "2016",

month = mar,

day = "7",

doi = "10.1109/ASPDAC.2016.7427981",

language = "English",

isbn = "9781467395694",

volume = "25-28-January-2016",

pages = "19--20",

booktitle = "2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016",

publisher = "IEEE",

address = "United States",

note = "21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 ; Conference date: 25-01-2016 Through 28-01-2016",

}

Lu, Q, Sham, CW & Lau, CM 2016, Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. vol. 25-28-January-2016, 7427981, IEEE, pp. 19-20, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, 25/01/16. https://doi.org/10.1109/ASPDAC.2016.7427981

Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard. / Lu, Qing; Sham, Chiu Wing; Lau, Chung Ming.
2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Vol. 25-28-January-2016 IEEE, 2016. p. 19-20 7427981.

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

TY - GEN

T1 - Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard

AU - Lu, Qing

AU - Sham, Chiu Wing

AU - Lau, Chung Ming

PY - 2016/3/7

Y1 - 2016/3/7

N2 - A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased to range from 382 MHz to 1852 MHz.

AB - A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased to range from 382 MHz to 1852 MHz.

UR - https://www.scopus.com/pages/publications/84996843680

U2 - 10.1109/ASPDAC.2016.7427981

DO - 10.1109/ASPDAC.2016.7427981

M3 - Conference article published in proceeding or book

SN - 9781467395694

VL - 25-28-January-2016

SP - 19

EP - 20

BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016

PB - IEEE

T2 - 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016

Y2 - 25 January 2016 through 28 January 2016

ER -

Rapid prototyping of multi-mode QC-LDPC decoder for 802.11n/ac standard

Abstract

Conference

ASJC Scopus subject areas

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