Abstract
A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased to range from 382 MHz to 1852 MHz.
Original language | English |
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Title of host publication | 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 |
Publisher | IEEE |
Pages | 19-20 |
Number of pages | 2 |
Volume | 25-28-January-2016 |
ISBN (Electronic) | 9781467395694 |
DOIs | |
Publication status | Published - 7 Mar 2016 |
Event | 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao Duration: 25 Jan 2016 → 28 Jan 2016 |
Conference
Conference | 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 |
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Country/Territory | Macao |
City | Macao |
Period | 25/01/16 → 28/01/16 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Science Applications
- Computer Graphics and Computer-Aided Design