Raised S/D gate-all-around CMOS using MILC

Chunshan Yin; Philip Ching Ho Chan; Victor W C Chan

Raised S/D gate-all-around CMOS using MILC

Chunshan Yin, Philip Ching Ho Chan, Victor W C Chan

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

Abstract

Complementary metal oxide semiconductor (CMOS) gate-all-around transistors (GAT) with raised S/D was demonstrated. Steeper sub-threshold slope, better suppressing of drain-induced-barrier-lowering (DIBL) and short-channel-effect (SCE), higher drive current were achieved in the fabricated GAT. The effect of double gate misalignment on Id-Vd characteristic was studied. Working CMOS GAT inverter showed steeper transfer characteristics.

Original language	English
Title of host publication	IEEE International SOI Conference
Pages	39-40
Number of pages	2
Publication status	Published - 1 Jan 2002
Externally published	Yes
Event	IEEE International SOI Conference - Williamsburg, VA, United States Duration: 7 Oct 2002 → 10 Oct 2002

Conference

Conference	IEEE International SOI Conference
Country/Territory	United States
City	Williamsburg, VA
Period	7/10/02 → 10/10/02

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@inproceedings{20c0a58c6a044953bc5901f81ee196c4,

title = "Raised S/D gate-all-around CMOS using MILC",

abstract = "Complementary metal oxide semiconductor (CMOS) gate-all-around transistors (GAT) with raised S/D was demonstrated. Steeper sub-threshold slope, better suppressing of drain-induced-barrier-lowering (DIBL) and short-channel-effect (SCE), higher drive current were achieved in the fabricated GAT. The effect of double gate misalignment on Id-Vd characteristic was studied. Working CMOS GAT inverter showed steeper transfer characteristics.",

author = "Chunshan Yin and Chan, \{Philip Ching Ho\} and Chan, \{Victor W C\}",

year = "2002",

month = jan,

day = "1",

language = "English",

pages = "39--40",

booktitle = "IEEE International SOI Conference",

note = "IEEE International SOI Conference ; Conference date: 07-10-2002 Through 10-10-2002",

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TY - GEN

T1 - Raised S/D gate-all-around CMOS using MILC

AU - Yin, Chunshan

AU - Chan, Philip Ching Ho

AU - Chan, Victor W C

PY - 2002/1/1

Y1 - 2002/1/1

N2 - Complementary metal oxide semiconductor (CMOS) gate-all-around transistors (GAT) with raised S/D was demonstrated. Steeper sub-threshold slope, better suppressing of drain-induced-barrier-lowering (DIBL) and short-channel-effect (SCE), higher drive current were achieved in the fabricated GAT. The effect of double gate misalignment on Id-Vd characteristic was studied. Working CMOS GAT inverter showed steeper transfer characteristics.

AB - Complementary metal oxide semiconductor (CMOS) gate-all-around transistors (GAT) with raised S/D was demonstrated. Steeper sub-threshold slope, better suppressing of drain-induced-barrier-lowering (DIBL) and short-channel-effect (SCE), higher drive current were achieved in the fabricated GAT. The effect of double gate misalignment on Id-Vd characteristic was studied. Working CMOS GAT inverter showed steeper transfer characteristics.

UR - https://www.scopus.com/pages/publications/0036458718

M3 - Conference article published in proceeding or book

SP - 39

EP - 40

BT - IEEE International SOI Conference

T2 - IEEE International SOI Conference

Y2 - 7 October 2002 through 10 October 2002

ER -

Raised S/D gate-all-around CMOS using MILC

Abstract

Conference

ASJC Scopus subject areas

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