Raised S/D gate-all-around CMOS using MILC

Chunshan Yin, Philip Ching Ho Chan, Victor W C Chan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

Abstract

Complementary metal oxide semiconductor (CMOS) gate-all-around transistors (GAT) with raised S/D was demonstrated. Steeper sub-threshold slope, better suppressing of drain-induced-barrier-lowering (DIBL) and short-channel-effect (SCE), higher drive current were achieved in the fabricated GAT. The effect of double gate misalignment on Id-Vd characteristic was studied. Working CMOS GAT inverter showed steeper transfer characteristics.
Original languageEnglish
Title of host publicationIEEE International SOI Conference
Pages39-40
Number of pages2
Publication statusPublished - 1 Jan 2002
Externally publishedYes
EventIEEE International SOI Conference - Williamsburg, VA, United States
Duration: 7 Oct 200210 Oct 2002

Conference

ConferenceIEEE International SOI Conference
CountryUnited States
CityWilliamsburg, VA
Period7/10/0210/10/02

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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