PTL: PCM translation layer

Zili Shao, Naehyuck Chang, Nikil Dutt

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

16 Citations (Scopus)

Abstract

PCM (Phase Change Memory) has been used as NOR flash replacement in embedded systems, and poses interesting system-level challenges for transparent exploitation of these memory structures by embedded systems software. We propose such a system-level transparent framework, called PTL (PCM Translation Layer), to efficiently manage PCM. PTL's translation layer conceals the physical constraints of the PCM architecture so that embedded systems software can use PCMs in a transparent manner, while efficiently exploiting the idiosyncrasies of the PCM architecture. We study the requirements for transparently managing PCM in embedded systems, and propose the system architecture of PTL. As a case study, we propose a simple yet effective wear leaveling technique by exploiting application-specific features in embedded systems. The experimental results show that our wear leveling technique can effectively improve the lifetime of PCM chips compared with the previous work. We expect this work can serve as a first step towards the full exploration of PCM in embedded systems.
Original languageEnglish
Title of host publicationProceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages380-385
Number of pages6
DOIs
Publication statusPublished - 29 Oct 2012
Event2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States
Duration: 19 Aug 201221 Aug 2012

Conference

Conference2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
CountryUnited States
CityAmherst, MA
Period19/08/1221/08/12

Keywords

  • PCM (Phase Change Memory)

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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