Abstract
In this article, we introduce an automatic stream computing reoptimization flow from ASICs to field-programmable gate arrays (FPGAs). Complex VLSI designs need to be prototyped and/or emulated on FPGAs. The main problem that we address in this article is that configurations optimized when targeting ASICs are often, as we will show in this article, highly un-optimal when remapped onto an FPGA. Thus, this article proposes a method to first generate a variety of dataflow configurations targeting an ASIC given multiple behavioral descriptions for high-level synthesis (HLS) and then, based on a compositional predictive model, automatically reoptimize the dataflow when mapped onto an FPGA. The experimental results show that our proposed method works well and that it is very fast.
Original language | English |
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Article number | 8957671 |
Pages (from-to) | 2615-2627 |
Number of pages | 13 |
Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Volume | 39 |
Issue number | 10 |
DOIs | |
Publication status | Published - Oct 2020 |
Keywords
- ASICs
- dataflow
- field-programmable gate arrays (FPGAs)
- high-level synthesis (HLS)
- predictive models (PMs)
- stream computing
ASJC Scopus subject areas
- Software
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering