Abstract
During the qualification of the 0.18um process technology, severe yield loss due to random single bit and dual bit failures were encountered. Though bit mapping using the MOSAID tester always identified the bit location, the failure analysis was still difficult due to the increasing susceptibility of 0.18-micron devices to the fluctuation of device parameters and process related defects. Furthermore, the increasing complexity and the multiple metal layers with stacked via structure made FA even tougher.
Original language | English |
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Title of host publication | Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA |
Pages | 117-120 |
Number of pages | 4 |
Publication status | Published - 1 Jan 2001 |
Externally published | Yes |
Event | 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore Duration: 9 Jul 2001 → 13 Jul 2001 |
Conference
Conference | 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) |
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Country/Territory | Singapore |
City | Singapure |
Period | 9/07/01 → 13/07/01 |
ASJC Scopus subject areas
- General Engineering