Poly-residue-induced contact failures in 0.18um technology

C. S. Teh, Z. G. Song, Jiyan Dai, Z. R. Guo, S. Redkar

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

5 Citations (Scopus)

Abstract

During the qualification of the 0.18um process technology, severe yield loss due to random single bit and dual bit failures were encountered. Though bit mapping using the MOSAID tester always identified the bit location, the failure analysis was still difficult due to the increasing susceptibility of 0.18-micron devices to the fluctuation of device parameters and process related defects. Furthermore, the increasing complexity and the multiple metal layers with stacked via structure made FA even tougher.
Original languageEnglish
Title of host publicationProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Pages117-120
Number of pages4
Publication statusPublished - 1 Jan 2001
Externally publishedYes
Event8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore
Duration: 9 Jul 200113 Jul 2001

Conference

Conference8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
Country/TerritorySingapore
CitySingapure
Period9/07/0113/07/01

ASJC Scopus subject areas

  • Engineering(all)

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