Physically based compact device model for fully depleted and nearly fully depleted SOI MOSFET

Srinivasa R. Banna, Philip Ching Ho Chan, Mansun Chan, Ping K. Ko

Research output: Journal article publicationJournal articleAcademic researchpeer-review

15 Citations (Scopus)


A compact submicrometer Fully Depleted Silicon-On-Insulator (FDSOI) and Nearly FDSOI MOSFET device model suitable for analog as well as digital application has been proposed. It is an all region model. In developing this model care has been taken in retaining the basic functional form of physical models while improving the model accuracy and computational efficiency. In addition to the commonly included effects in the FDSOI MOSFET model, we have given careful consideration to parasitic source/drain resistance, Drain Induced Conductivity Enhancement (DICE) effect, floating body effect, self-heating and model continuity. A single parameter set is used for a large set of device dimensions except threshold voltage and parasitic source/drain resistance due to silicon film thickness variations. The accuracy of the model is validated with experimental data using NMOS FDSOI devices and found to be in good agreement.
Original languageEnglish
Pages (from-to)1914-1923
Number of pages10
JournalIEEE Transactions on Electron Devices
Issue number11
Publication statusPublished - 1 Nov 1996
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)


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