Performance optimization of multiple memory architectures for DSP

Keyphrases

• Multiple Memories 100%
• Performance Optimization 100%
• Memory Architecture 100%
• Graph Model 75%
• Variable Partitioning 75%
• High Performance 50%
• Schedule Length 50%
• Memory Module 50%
• Feasible Solution 25%
• Memory Access 25%
• Experiment Results 25%
• Scheduling Algorithm 25%
• Scheduling Process 25%
• Software pipeline 25%
• Interference Graph 25%
• Module Architecture 25%
• Scheduling Techniques 25%
• Partition Problem 25%
• Independence Graph 25%
• Variable Independence 25%
• Retiming 25%
• Design Space Exploration 25%
• Rotation Schedule 25%

Computer Science

• Memory Multiple 100%
• Performance Optimization 100%
• Memory Architecture 100%
• Memory Access 50%
• Scheduling Algorithm 50%
• Scheduling Process 50%
• Interference Graph 50%
• Design-Space Exploration 50%
• Software Pipelining 50%
• Feasible Solution 50%
• Functional Unit 50%