Parallel electronic circuit simulation on the IPSC system.

Chen Ping Yuan; Robert Lucas; Philip Ching Ho Chan; Robert Dutton

Parallel electronic circuit simulation on the IPSC system.

Chen Ping Yuan, Robert Lucas, Philip Ching Ho Chan, Robert Dutton

Research output: Journal article publication › Conference article › Academic research › peer-review

Abstract

A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.

Original language	English
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1 Dec 1988
Externally published	Yes
Event	Proceedings of the IEEE 1988 Custom Integrated Circuits Conference. - Rochester, NY, United States Duration: 1 Dec 1988 → …

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

@article{c190519f36b74876b872cede0283f5ba,

title = "Parallel electronic circuit simulation on the IPSC system.",

abstract = "A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.",

author = "Yuan, {Chen Ping} and Robert Lucas and Chan, {Philip Ching Ho} and Robert Dutton",

year = "1988",

month = dec,

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language = "English",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "Proceedings of the IEEE 1988 Custom Integrated Circuits Conference. ; Conference date: 01-12-1988",

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T1 - Parallel electronic circuit simulation on the IPSC system.

AU - Yuan, Chen Ping

AU - Lucas, Robert

AU - Chan, Philip Ching Ho

AU - Dutton, Robert

PY - 1988/12/1

Y1 - 1988/12/1

N2 - A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.

AB - A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.

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M3 - Conference article

SN - 0886-5930

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

T2 - Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

Y2 - 1 December 1988

ER -

Parallel electronic circuit simulation on the IPSC system.

Abstract

ASJC Scopus subject areas

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