Parallel electronic circuit simulation on the IPSC system.

Chen Ping Yuan, Robert Lucas, Philip Ching Ho Chan, Robert Dutton

Research output: Journal article publicationConference articleAcademic researchpeer-review

5 Citations (Scopus)


A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.
Original languageEnglish
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1 Dec 1988
Externally publishedYes
EventProceedings of the IEEE 1988 Custom Integrated Circuits Conference. - Rochester, NY, United States
Duration: 1 Dec 1988 → …

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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