A parallel circuit simulator was implemented on the iPSC system. Concurrent model evaluation, hierarchical BBDF (bordered block diagonal form) reordering, and distributed multifrontal decomposition to solve the sparse matrix are used. A speedup of six times has been achieved on an eight-processor iPSC hypercube system.
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 1 Dec 1988|
|Event||Proceedings of the IEEE 1988 Custom Integrated Circuits Conference. - Rochester, NY, United States|
Duration: 1 Dec 1988 → …
ASJC Scopus subject areas
- Electrical and Electronic Engineering