Abstract
Recently, there have been different applications, namely 10GBase-T Ethernet, video broadcasting and satellite communication, utilizing low-density parity-check (LDPC) codes as the forward-error-correction codes. The main reason is that the error performance of LDPC codes can be very close to the Shannon limit. LDPC codes can be further categorized into LDPC block codes (LDPC-BCs) and LDPC convolutional codes (LDPC-CCs). It has also been discovered that LDPC-CCs usually outperform LDPC-BCs. Simulation of LDPC-BCs and LDPC-CCs can take a lot of time because the decoding algorithms are relatively complex. Fortunately, the decoding steps can be performed in parallel. In this paper, we create three different platforms for simulating the error performance of LDPC-CCs. The first two platforms are run on a Central Processing Unit (CPU) while the third one involves the use of a Graphics Processing Unit (GPU). We show that using GPU can improve the simulation speed substantially.
Original language | English |
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Title of host publication | 2012 IEEE Symposium on Computers and Communications, ISCC 2012 |
Pages | 000225-000227 |
DOIs | |
Publication status | Published - 28 Sept 2012 |
Event | 17th IEEE Symposium on Computers and Communication, ISCC 2012 - Cappadocia, Turkey Duration: 1 Jul 2012 → 4 Jul 2012 |
Conference
Conference | 17th IEEE Symposium on Computers and Communication, ISCC 2012 |
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Country/Territory | Turkey |
City | Cappadocia |
Period | 1/07/12 → 4/07/12 |
Keywords
- CPU
- error performance
- GPU
- LDPC code
- LDPC convolutional code
ASJC Scopus subject areas
- Computer Networks and Communications
- Computer Science Applications
- Software
- General Mathematics
- Signal Processing