Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units

Chun Xue, Zili Shao, Oingfeng Zhuae, Edwin H.M. Sha, Bin Xiao, Meilin Liu, Edwin H.M. Sha

Research output: Journal article publicationJournal articleAcademic researchpeer-review

8 Citations (Scopus)


Digital signal processors provide dedicated address generation units (AGUs) that are capable of performing address arithmetic in parallel to the main data path. Address assignment, optimization of memory layout of program variables to reduce address arithmetic instructions by taking advantage of the capabilities of AGUs, has been studied extensively for single-functional-unit (FU) processors. In this brief, we exploit address assignment and scheduling for multiple-FU processors. We propose an efficient address assignment and scheduling algorithm for multiple-FU processors. Experimental results show that our algorithm can greatly reduce schedule length and address operations on multiple-FU processors compared with the previous work.
Original languageEnglish
Pages (from-to)976-980
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number9
Publication statusPublished - 1 Jan 2006


  • Address assignment
  • address generation unit (AGU)
  • digital signal processor (DSP)
  • multiple functional units(FUs)
  • scheduling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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