Optimization of stencil printing wafer bumping for fine pitch flip chip applications

Jing Feng Gong, Esther W C Yau, Philip Ching Ho Chan, Ricky S W Lee, Matthew M F Yuen

Research output: Journal article publicationConference articleAcademic researchpeer-review

4 Citations (Scopus)

Abstract

Stencil printing wafer bumping offers the advantages of low-cost and compatibility with the traditional surface mount assembly equipment. To achieve high quality fine pitch stencil printing wafer bumping, many process parameters need to be optimized. This paper focuses on the optimization of the static and dynamic process parameters for fine pitch flip chip applications. It was found the static parameters have significant effect on the yield of stencil printing process. High printing yield can be achieved by the sound stencil design strategies. The solder paste selection is also critical to the printing quality. Type 6 solder paste produces better printing results. A two level L8 orthogonal array Taguchi experiment was designed and carried out to evaluate the dynamic parameters including squeegee pressure, print speed, separation speed and print gap. Stencil printing quality, solder paste transfer efficiency (TE) and defects rate were measured. The transfer efficiency is defined as the ratio of solder paste volume to the aperture volume. The analysis of variance (ANOVA) based on mean and signal to noise ratio (S/N) were performed using Qualitek-4 software to find out the optimum values of process parameters.
Original languageEnglish
Pages (from-to)1724-1730
Number of pages7
JournalProceedings - Electronic Components and Technology Conference
Publication statusPublished - 17 Jul 2003
Externally publishedYes
Event53rd Electronic Components and Technology Conference 2003 - New Orleans LA, United States
Duration: 27 May 200330 May 2003

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this