Operating frequency improvement on FPGA implementation of a pipeline large-FFT processor

Ting Wai Siu, Chiu Wing Sham, Chung Ming Lau

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

4 Citations (Scopus)


In this paper, circuit complexity reduction in FPGA implementation of large N-point Radix-22FFT with single-path delay feedback architecture is reported. Memory requirement of the FFT in the FPGA consists of two parts, the RAM data storage of the feedback in each stage of the data flow and the twiddle factors prepared as ROM for each complex multiplication. Through address rearrangement, the ROM sizes for the twiddle factors are significantly reduced with the removal of redundancy. The reduction ratio is about 1/3(log4N-1). As a result, the signal critical path is reduced and the system clock frequency is increased. The proposed architecture is validated by the implementations of 1K and 4K Radix-22FFTs in an Altera Cyclone IV FPGA, EP4CGX22, which is the second lowest capacity FPGA of the low cost series. For the 1K- and 4K-point FFTs, the operating frequencies are 231.11 MHz and 215.75 MHz, respectively, approaching 250 MHz which is the speed limit of the I/O ports of the FPGA [1].
Original languageEnglish
Title of host publication19th International Conference on Advanced Communications Technology
Subtitle of host publicationOpening Era of Smart Society, ICACT 2017 - Proceeding
Number of pages5
ISBN (Electronic)9788996865094
Publication statusPublished - 29 Mar 2017
Event19th International Conference on Advanced Communications Technology, ICACT 2017 - Phoenix Park, Pyeongchang, Korea, Republic of
Duration: 19 Feb 201722 Feb 2017


Conference19th International Conference on Advanced Communications Technology, ICACT 2017
Country/TerritoryKorea, Republic of


  • 1K-FFT
  • 4K-FFT
  • Fast fourier transform implementation
  • FPGA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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