On using the cyclically-coupled QC-LDPC codes in future SSDs

Keyphrases

• Low-density Parity-check Codes 100%
• Solid State Drive 100%
• Error Correction 33%
• Error Rate 33%
• Block Codes 33%
• Clock Frequency 33%
• Decoder 33%
• Technology Upgrading 33%
• Implementation Barriers 33%
• Flash Memory 33%
• Capacity Scaling 33%
• Encoder-decoder Architecture 33%
• BCH Codes 33%
• FPGA Implementation 33%
• Decoding Ability 33%

Computer Science

• Solid State Drive 100%
• low-density parity-check code 100%
• Flash Memory 50%
• Participatory Design 50%
• Decoding Ability 50%
• Error Correction 50%

Engineering

• Parity Check Code 100%
• Field Programmable Gate Arrays 50%
• Clock Rate 50%
• Error Correction 50%
• Error Rate 50%
• Block Code 50%
• Flash Memory 50%