On using the cyclically-coupled QC-LDPC codes in future SSDs

Qing Lu, Chiu Wing Sham, Chung Ming Lau

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

3 Citations (Scopus)

Abstract

As the flash memory continues its capacity scaling and correspondingly decreases its reliability, a technology upgrade regarding the error-correction engine in state-of-art solid-state drives (SSDs) is intensely expected. Due to their limit-approaching decoding ability, low-density parity-check (LDPC) codes are seen as one of the most promising substitute for the traditional BCH codes, though implementation barriers remain to degrade their performance. In our recent work, a co-design of LDPC block codes and their decoder architecture are developed and found suitable to apply to address these barriers with an overall excellence in error rate, complexity as well as throughput. Four codes of 4 KB and 4/5 rate are proposed and their FPGA-based implementations are conducted. It is shown that the decoders reach 1.47 Gb/s throughput at 100 MHz clock rates, and their complexity are estimated to be 1 million gates with 1 Mb memory.
Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherIEEE
Pages625-628
Number of pages4
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 3 Jan 2017
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 25 Oct 201628 Oct 2016

Conference

Conference2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Country/TerritoryKorea, Republic of
CityJeju
Period25/10/1628/10/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing

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