On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter

Wei Jin, Philip Ching Ho Chan, Mansun Chan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

1 Citation (Scopus)

Abstract

The leakage current due to the parasitic PN junction diodes in SOI DTMOS (Dynamic Threshold Voltage MOSFET) inverter is reported. The additional power dissipation in DTMOS inverter due to the diodes is quantified through an analytical model and verified by MEDICI simulation. Power dissipation between conventional SOI CMOS and SOI DTMOS inverters is compared.
Original languageEnglish
Title of host publicationInternational Symposium on Low Power Electronics and Design, Digest of Technical Papers
PublisherIEEE
Pages247-250
Number of pages4
Publication statusPublished - 1 Jan 1997
Externally publishedYes
EventProceedings of the 1997 International Symposium on Low Power Electronics and Design - Monterey, CA, United States
Duration: 18 Aug 199720 Aug 1997

Conference

ConferenceProceedings of the 1997 International Symposium on Low Power Electronics and Design
Country/TerritoryUnited States
CityMonterey, CA
Period18/08/9720/08/97

ASJC Scopus subject areas

  • Engineering(all)

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