On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter

Wei Jin, Philip Ching Ho Chan, Mansun Chan

Research output: Journal article publicationJournal articleAcademic researchpeer-review

8 Citations (Scopus)


A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V.
Original languageEnglish
Pages (from-to)1717-1724
Number of pages8
JournalIEEE Transactions on Electron Devices
Issue number8
Publication statusPublished - 1 Dec 1998
Externally publishedYes


  • Dynamic threshold-voltage mosfet (dtmos)
  • Power dissipation
  • Silicon-on-insulator (soi)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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