NVMcached: An NVM-based key-value cache

Xingbo Wu, Fan Ni, Li Zhang, Yandong Wang, Yufei Ren, Michel Hack, Zili Shao, Song Jiang

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

28 Citations (Scopus)


As byte-addressable, high-density, and non-volatile memory (NVM) is around the corner to be equipped alongside the DRAM memory, issues on enabling the important key-value cache services, such as memcached, on the new storage medium must be addressed. While NVM allows data in a KV cache to survive power outage and system crash, in practice their integrity and accessibility depend on data consistency enforced during writes to NVM. Though techniques for enforcing the consistency, such as journaling, COW, or checkpointing, are available , they are often too expensive by frequently using CPU cache flushes to ensure crash consistency, leading to (much) reduced performance and excessively compromised NVM's lifetime. In this paper we design and evaluate NVMcached, a KV cache for non-volatile byte-addressable memory that can significantly reduce use of flushes and minimize data loss by leveraging consistency-friendly data structures and batched space allocation and reclamation. Experiments show that NVMcached can improve its system throughput by up to 2.8x for write-intensive real-world workloads, compared to a non-volatile memcached.
Original languageEnglish
Title of host publicationProceedings of the 7th ACM SIGOPS Asia-Pacific Workshop on Systems, APSys 2016
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450342650
Publication statusPublished - 4 Aug 2016
Event7th ACM SIGOPS Asia-Pacific Workshop on Systems, APSys 2016 - Hong Kong, Hong Kong
Duration: 4 Aug 20165 Aug 2016


Conference7th ACM SIGOPS Asia-Pacific Workshop on Systems, APSys 2016
Country/TerritoryHong Kong
CityHong Kong

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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