Novel local silicon-gate carbon nanotube transistors combining silicon-on-insulator technology for integration

Min Zhang, Philip Ching Ho Chan, Yang Chai, Qi Liang, Z. K. Tang

Research output: Journal article publicationJournal articleAcademic researchpeer-review

7 Citations (Scopus)


By taking advantage of the silicon-on-insulator technology and the in situ carbon nanotube (CNT) growth, new local silicon-gate carbon nanotube FETs (CNFETs) have been implemented in this paper. We propose an approach to integrate the CNFET onto the silicon CMOS platform for the first time. Individual device operation, batch fabrication, low parasitic capacitance, and better compatibility to the CMOS process were realized. The characteristics of the CNFETs are comparable to the state-of-the-art devices reported. The scaling effect, ambipolar conductance, Schottky barrier effect, and IV characteristics noise were analyzed. The physical properties of the CNTs were also characterized.
Original languageEnglish
Article number4749330
Pages (from-to)260-268
Number of pages9
JournalIEEE Transactions on Nanotechnology
Issue number2
Publication statusPublished - 1 Mar 2009
Externally publishedYes


  • Carbon nanotube (CNT)
  • Carbon nanotube FET (CNFET)
  • Integration
  • Nanotechnology
  • Silicon-on-insulator (SOI)

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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