Abstract
A new algorithm is introduced such that one can convert an odd prime length, N, discrete cosine transform (DCT) into two (N-1)/2 length cyclic correlations. This formulation enables realization of the DCT by using distributed arithmetic and it also results in an extremely regular structure which is most suitable for VLSI realization. The proposed algorithm can be realized efficiently and easily by dedicated hardware or gate array technology. The structure of the hardware required is so simple that it involves only memory and adders. This can achieve a high performance DCT chip at a minimum cost and development time. An example is given to show the feasibility and the structural regularity of the algorithm.
Original language | English |
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Title of host publication | 90 IEEE Reg 10 Conf Comput Commun Syst IEEE TENCON 91 |
Publisher | Publ by IEEE |
Pages | 190-193 |
Number of pages | 4 |
ISBN (Print) | 0879425563 |
Publication status | Published - 1 Jan 1991 |
Event | 1990 IEEE Region 10 Conference on Computer and Communication Systems - IEEE TENCON '90 - , Hong Kong Duration: 24 Sept 1990 → 27 Sept 1990 |
Conference
Conference | 1990 IEEE Region 10 Conference on Computer and Communication Systems - IEEE TENCON '90 |
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Country/Territory | Hong Kong |
Period | 24/09/90 → 27/09/90 |
ASJC Scopus subject areas
- General Engineering