New storage scheme for conflict-free vector access

Kin Man Lam; Wan Chi Siu; Jun Xun Yin; Kai Ming Tse

New storage scheme for conflict-free vector access

Kin Man Lam, Wan Chi Siu, Jun Xun Yin, Kai Ming Tse

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

Abstract

Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved scheme, skewed scheme and XOR scheme. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.

Original language	English
Title of host publication	Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering
Publisher	Publ by IEEE
Pages	32-35
Number of pages	4
ISBN (Print)	0780312333
Publication status	Published - 1 Dec 1993
Event	Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) - Beijing, China Duration: 19 Oct 1993 → 21 Oct 1993

Conference

Conference	Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5)
Country/Territory	China
City	Beijing
Period	19/10/93 → 21/10/93

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "New storage scheme for conflict-free vector access",

abstract = "Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved scheme, skewed scheme and XOR scheme. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.",

author = "Lam, {Kin Man} and Siu, {Wan Chi} and Yin, {Jun Xun} and Tse, {Kai Ming}",

year = "1993",

month = dec,

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pages = "32--35",

booktitle = "Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering",

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note = "Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) ; Conference date: 19-10-1993 Through 21-10-1993",

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Lam, KM, Siu, WC, Yin, JX & Tse, KM 1993, New storage scheme for conflict-free vector access. in Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering. Publ by IEEE, pp. 32-35, Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5), Beijing, China, 19/10/93.

New storage scheme for conflict-free vector access. / Lam, Kin Man; Siu, Wan Chi; Yin, Jun Xun et al.

Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering. Publ by IEEE, 1993. p. 32-35.

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

TY - GEN

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AU - Siu, Wan Chi

AU - Yin, Jun Xun

AU - Tse, Kai Ming

PY - 1993/12/1

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N2 - Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved scheme, skewed scheme and XOR scheme. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.

AB - Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved scheme, skewed scheme and XOR scheme. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.

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M3 - Conference article published in proceeding or book

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BT - Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering

PB - Publ by IEEE

T2 - Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5)

Y2 - 19 October 1993 through 21 October 1993

ER -

New storage scheme for conflict-free vector access

Abstract

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ASJC Scopus subject areas

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