New storage scheme for conflict-free vector access

Kin Man Lam, Wan Chi Siu, Jun Xun Yin, Kai Ming Tse

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

Abstract

Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved scheme, skewed scheme and XOR scheme. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.
Original languageEnglish
Title of host publicationProceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering
PublisherPubl by IEEE
Pages32-35
Number of pages4
ISBN (Print)0780312333
Publication statusPublished - 1 Dec 1993
EventProceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) - Beijing, China
Duration: 19 Oct 199321 Oct 1993

Conference

ConferenceProceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5)
CountryChina
CityBeijing
Period19/10/9321/10/93

ASJC Scopus subject areas

  • Engineering(all)

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