Abstract
This paper presents new insights into board level drop impact using analytical relations that have been developed. The dominance of bending moment as a failure driver leads naturally to the dynamic-static analysis technique, which together with the dominance of fundamental flexing mode led to a simple relation for interconnection stress. Using this relation, it has been found that miniaturisation of interconnection with accompanying reduction in load bearing area is the most significant source of drop impact vulnerability. Finally, a low cost PCB has been proposed with equivalent dynamic characteristic and near equivalent interconnection stress as the eight-layer microvia board specified in JEDEC Std JESD22-B111.
Original language | English |
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Pages (from-to) | 930-938 |
Number of pages | 9 |
Journal | Microelectronics Reliability |
Volume | 46 |
Issue number | 5-6 |
DOIs | |
Publication status | Published - May 2006 |
Externally published | Yes |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Condensed Matter Physics
- Safety, Risk, Reliability and Quality
- Surfaces, Coatings and Films
- Electrical and Electronic Engineering