This letter presents a method to fabricate high performance three-dimensional (3-D) integrated circuits based on the conventional CMOS SOI technology. The first layer of transistors is fabricated on SOI and the second layer is fabricated on large-grain polysilicon-on-insulator (LPSOI), using oxide as the interlayer dielectric. The LPSOI film is formed by the recrystallization of amorphous silicon through metal induced lateral crystallization (MILC). The grain size obtained by the LPSOI process is much larger than the transistors and the transistor performance is similar to those fabricated on the SOI layer. The three-dimensional (3-D) CMOS inverters have been demonstrated with p-channel devices stacking over the n-channel ones.
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering