MNFTL: An efficient flash translation layer for MLC NAND flash memory storage systems

Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, Yong Guan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

91 Citations (Scopus)


The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.
Original languageEnglish
Title of host publication2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Number of pages6
Publication statusPublished - 16 Sep 2011
Event2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States
Duration: 5 Jun 20119 Jun 2011


Conference2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Country/TerritoryUnited States
CitySan Diego, CA


  • Address mapping
  • Flash translation layer
  • Garbage collection
  • MLC NAND flash memory

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

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