Abstract
The new write constraints of multi-level cell (MLC) NAND flash memory make most of the existing flash translation layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC flash translation layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.
Original language | English |
---|---|
Title of host publication | 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 |
Pages | 17-22 |
Number of pages | 6 |
Publication status | Published - 16 Sept 2011 |
Event | 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States Duration: 5 Jun 2011 → 9 Jun 2011 |
Conference
Conference | 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 |
---|---|
Country/Territory | United States |
City | San Diego, CA |
Period | 5/06/11 → 9/06/11 |
Keywords
- Address mapping
- Flash translation layer
- Garbage collection
- MLC NAND flash memory
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modelling and Simulation