Minimizing leakage energy with modulo scheduling for VLIW DSP processors

Keyphrases

• Scheduling Algorithm 100%
• DSP Processor 100%
• VLIW DSP 100%
• Leakage Energy 100%
• Trimaran 100%
• Leakage Energy Saving 100%
• Modulo Scheduling 100%
• Compiler 50%
• Nanometre 50%
• Total Energy Consumption 50%
• Management Scheme 50%
• Scaling Approach 50%
• Mibench 50%
• DSP Applications 50%
• VLIW Architecture 50%
• Active Mode 50%
• Leakage Power 50%
• Idleness 50%
• Sleep Mode 50%
• Function Unit 50%
• Leakage Management 50%
• Technology Scaling 50%

Computer Science

• Scheduling Algorithm 100%
• Modulo Scheduling 100%
• Power Consumption 50%