Minimizing leakage energy with modulo scheduling for VLIW DSP processors

Meng Wang, Zili Shao, Hui Liu, Chun Jason Xue

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

2 Citations (Scopus)


As technology scaling approaches to the nanometer, leakage power has become a significant component of the total power consumption. In this paper, we develop a novel leakage-aware modulo scheduling algorithm to achieve leakage energy savings for DSP applications with loops on VLIW architecture. The proposed algorithm is designed to maximize the idleness of function units integrating with leakage management scheme [9], and reduce the number of transitions between active and sleep modes. We have implemented our technique into the Trimaran compiler [1] and conducted experiments using a set of benchmarks from DSPstone [11] and Mibench [7] on the VLIW simulator of Trimaran. The results show that our algorithm achieves significant leakage energy savings compared with the leakageaware scheduling algorithm [8].
Original languageEnglish
Title of host publicationDistributed Embedded Systems
Subtitle of host publicationDesign, Middleware and Resources
Number of pages10
Publication statusPublished - 21 Jul 2008

Publication series

NameIFIP International Federation for Information Processing
ISSN (Print)1571-5736

ASJC Scopus subject areas

  • Information Systems and Management

Cite this