Memory access aware mapping for networks-on-chip

Xi Jin, Nan Guan, Qingxu Deng, Wang Yi

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

4 Citations (Scopus)

Abstract

Networks-on-Chip (NoC) has been introduced to offer high on-chip communication bandwidth for large-scale multi-core systems. However, the communication bandwidth between NoC chips and off-chip memories is relatively low, which seriously limits the overall system performance. So optimizing the off-chip memory communication efficiency is a crucial issue in the NoC system design flow. In this paper, we present a memory access aware mapping algorithm for NoC, which explores SDRAM access parallelization in order to offer higher off-chip memory communication efficiency, and eventually achieve higher overall system performance. To the best of our knowledge, this is the first work to consider off-chip memory communication efficiency in application mapping on NoC. Experimental results showed that, comparing with classical NoC mapping algorithms, our algorithm can significantly improve the memory utilization and overall system throughput (on average 60% improvement).
Original languageEnglish
Title of host publicationProceedings - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
Pages339-348
Number of pages10
Volume1
DOIs
Publication statusPublished - 1 Dec 2011
Externally publishedYes
Event17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 - Toyama, Japan
Duration: 28 Aug 201131 Aug 2011

Conference

Conference17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
CountryJapan
CityToyama
Period28/08/1131/08/11

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Computer Science Applications

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