Abstract
Networks-on-Chip (NoC) has been introduced to offer high on-chip communication bandwidth for large-scale multi-core systems. However, the communication bandwidth between NoC chips and off-chip memories is relatively low, which seriously limits the overall system performance. So optimizing the off-chip memory communication efficiency is a crucial issue in the NoC system design flow. In this paper, we present a memory access aware mapping algorithm for NoC, which explores SDRAM access parallelization in order to offer higher off-chip memory communication efficiency, and eventually achieve higher overall system performance. To the best of our knowledge, this is the first work to consider off-chip memory communication efficiency in application mapping on NoC. Experimental results showed that, comparing with classical NoC mapping algorithms, our algorithm can significantly improve the memory utilization and overall system throughput (on average 60% improvement).
Original language | English |
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Title of host publication | Proceedings - 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 |
Pages | 339-348 |
Number of pages | 10 |
Volume | 1 |
DOIs | |
Publication status | Published - 1 Dec 2011 |
Externally published | Yes |
Event | 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 - Toyama, Japan Duration: 28 Aug 2011 → 31 Aug 2011 |
Conference
Conference | 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 |
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Country/Territory | Japan |
City | Toyama |
Period | 28/08/11 → 31/08/11 |
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Computer Networks and Communications
- Computer Science Applications