Low S/D resistance FDSOI MOSFETs using polysilicon and CMP

C. Yin; V. W C Chan; Philip Ching Ho Chan

Low S/D resistance FDSOI MOSFETs using polysilicon and CMP

C. Yin
, V. W C Chan
, Philip Ching Ho Chan

Research output: Chapter in book / Conference proceeding › Conference article published in proceeding or book › Academic research › peer-review

5 Citations (Scopus)

Abstract

In this paper, we report the fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.

Original language	English
Title of host publication	Proceedings of the IEEE Hong Kong Electron Devices Meeting
Pages	89-92
Number of pages	4
Publication status	Published - 1 Jan 2001
Externally published	Yes
Event	2001 IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong Duration: 30 Jun 2001 → …

Conference

Conference	2001 IEEE Hong Kong Electron Devices Meeting
Country/Territory	Hong Kong
City	Hong Kong
Period	30/06/01 → …

Keywords

CMOS
CMP
Fully depleted SOI
MOSFETs
Poly raised source/drain

ASJC Scopus subject areas

General Engineering

Cite this

@inproceedings{e048db9964a94eb88a7685384475f9f4,

title = "Low S/D resistance FDSOI MOSFETs using polysilicon and CMP",

abstract = "In this paper, we report the fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95\% reduction in source and drain series resistance and 90\% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.",

keywords = "CMOS, CMP, Fully depleted SOI, MOSFETs, Poly raised source/drain",

author = "C. Yin and Chan, \{V. W C\} and Chan, \{Philip Ching Ho\}",

year = "2001",

month = jan,

day = "1",

language = "English",

pages = "89--92",

booktitle = "Proceedings of the IEEE Hong Kong Electron Devices Meeting",

note = "2001 IEEE Hong Kong Electron Devices Meeting ; Conference date: 30-06-2001",

}

TY - GEN

T1 - Low S/D resistance FDSOI MOSFETs using polysilicon and CMP

AU - Yin, C.

AU - Chan, V. W C

AU - Chan, Philip Ching Ho

PY - 2001/1/1

Y1 - 2001/1/1

N2 - In this paper, we report the fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.

AB - In this paper, we report the fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.

KW - CMOS

KW - CMP

KW - Fully depleted SOI

KW - MOSFETs

KW - Poly raised source/drain

UR - https://www.scopus.com/pages/publications/0034828446

M3 - Conference article published in proceeding or book

SP - 89

EP - 92

BT - Proceedings of the IEEE Hong Kong Electron Devices Meeting

T2 - 2001 IEEE Hong Kong Electron Devices Meeting

Y2 - 30 June 2001

ER -

Low S/D resistance FDSOI MOSFETs using polysilicon and CMP

Abstract

Conference

Keywords

ASJC Scopus subject areas

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