Abstract
In this paper, we report the fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.
Original language | English |
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Title of host publication | Proceedings of the IEEE Hong Kong Electron Devices Meeting |
Pages | 89-92 |
Number of pages | 4 |
Publication status | Published - 1 Jan 2001 |
Externally published | Yes |
Event | 2001 IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong Duration: 30 Jun 2001 → … |
Conference
Conference | 2001 IEEE Hong Kong Electron Devices Meeting |
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Country/Territory | Hong Kong |
City | Hong Kong |
Period | 30/06/01 → … |
Keywords
- CMOS
- CMP
- Fully depleted SOI
- MOSFETs
- Poly raised source/drain
ASJC Scopus subject areas
- General Engineering