Low S/D resistance FDSOI MOSFETs using polysilicon and CMP

C. Yin, V. W C Chan, Philip Ching Ho Chan

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

4 Citations (Scopus)

Abstract

In this paper, we report the fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using Chemical Mechanical Polish (CMP). This poly raised FDSOI MOSFETs, with channel thickness of 30nm and deposited poly thickness of 80nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.
Original languageEnglish
Title of host publicationProceedings of the IEEE Hong Kong Electron Devices Meeting
Pages89-92
Number of pages4
Publication statusPublished - 1 Jan 2001
Externally publishedYes
Event2001 IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong
Duration: 30 Jun 2001 → …

Conference

Conference2001 IEEE Hong Kong Electron Devices Meeting
CountryHong Kong
CityHong Kong
Period30/06/01 → …

Keywords

  • CMOS
  • CMP
  • Fully depleted SOI
  • MOSFETs
  • Poly raised source/drain

ASJC Scopus subject areas

  • Engineering(all)

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