Low-power reconfigurable acceleration of robust frequency-domain echo cancellation on FPGA

Wai Chung Tang, C. H. Ho, Chiu Wing Sham, Ka Fai Cedric Yiu

Research output: Chapter in book / Conference proceedingConference article published in proceeding or bookAcademic researchpeer-review

2 Citations (Scopus)


Real time echo cancellation is an important feature for hands-free operation of telecommunication equipment like mobile phones. A desirable acoustic echo control should be capable of handling double-talk as well. In this paper, we successfully implement a novel hardware architecture that is based on a robust adaptive algorithm in combination with a two-path model to tackle the double-talk situation. The echo-canceller is working in the frequency domain and is improved by bitwidth optimization to enhance computational efficiency. In experiments, our implementation of the hardware acceleration of the echo-canceller is fast and outperforms common software implementations running on microprocessors: an implementation with 4 instances of the filter on a Xilinx XC4VFX60 FPGA running at 137MHz can run 40 times faster than software on a 3.2GHz Core 2 Duo PC. Besides, the hardware acceleration also reduces 90% of the power consumption when compared to a pure soft-core implementation. Our results suggest that the employed hardware architecture is also very energy-efficient.
Original languageEnglish
Title of host publication1st International Conference on Green Circuits and Systems, ICGCS 2010
Number of pages4
Publication statusPublished - 20 Sep 2010
Event1st International Conference on Green Circuits and Systems, ICGCS 2010 - Shanghai, China
Duration: 21 Jun 201023 Jun 2010


Conference1st International Conference on Green Circuits and Systems, ICGCS 2010

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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