Low power motion estimation based on probabilistic computing

As CMOS technology driven by Moore's law has approached device sizes in the range of 5-20 nm, noise immunity of such future technology nodes is predicted to decrease considerably, eventually affecting the reliability of computations through them. A shift in the design paradigm is expected from 100% accurate computations to probabilistic computing with accuracy dependent on the target application or circuit specifications. One model developed for CMOS technology that emulates the erroneous behavior predicted is termed probabilistic CMOS (PCMOS). In this paper, we propose a PCMOS-based architecture implementation for traditional motion estimation algorithms and show that up to 57% energy savings are possible for different existing motion estimation algorithms. Furthermore, algorithmic modifications are proposed that can enhance the energy savings to 70% with a PCMOS architectural implementation. About 1.8-5 dB improvement in peak signal-to-noise ratio under energy savings of 57% to 70% for two different motion estimation algorithms is shown, establishing the resilience of the proposed algorithm to probabilistic computing over the comparable conventional algorithm.